Metal-insulator-metal (MIM) capacitors are frequently employed in semiconductor dies to provide capacitance to circuitry on the semiconductor die. For example, MIM capacitors are added to semiconductor dies having radio frequency (RF) circuitry to provide bypass capacitance. MIM capacitors are increasingly used to improve performance of devices that operate at increasingly higher frequencies. However, the fabrication of MIM capacitors usually increases the cost of producing a semiconductor die by increasing the number of processing steps and increases the number of masks used to produce a die, for example.
MIM capacitors are usually formed between two interconnect metal layers of a semiconductor die. FIG. 1 is a cross-sectional view illustrating an example of a conventional MIM capacitor structure 100 on a semiconductor die. In the conventional MIM capacitor structure 100, a bottom node 102 and a top node 104 of a MIM capacitor are separated by a dielectric layer 106. The bottom node 102 and top node 104 of the MIM capacitor are built between a first metal (Mx) layer 108 and a second metal (Mx+1) layer 110 of the semiconductor die. The first metal layer 108 and second metal layer 110 are patterned by respective masks to build conventional distribution and interconnection paths on the die, for example. A first additional mask is used during a first additional patterning process to pattern the bottom node 102 of the MIM capacitor. A second additional mask is used during a second additional patterning step to pattern the top node 104 of the MIM capacitor.
A first layer (Vx) of conductive vias 112 may be formed to provide coupling or connection between the first metal layer 108 and the second metal layer 110. In this example of a conventional MIM capacitor structure 100, additional conductive vias 114, 116 are formed to couple the top node 104 of the MIM capacitor to one path of the second metal layer 110, and to couple the bottom node 102 to another path of the second metal layer 110.
FIG. 2 is a cross-sectional view illustrating another example of a conventional MIM capacitor structure 200 on a semiconductor die. In the conventional MIM capacitor structure 200, a bottom node 202 and a top node 204 of a MIM capacitor are separated by a dielectric layer 206. The bottom node 202 and top node 204 of the MIM capacitor are built between a first metal (Mx) layer 208 and a second metal (Mx+1) layer 210 of the semiconductor die. The first metal layer 208 and second metal layer 210 are patterned by respective masks to build conventional distribution and interconnection paths on the die, for example. A first additional mask is used during a first additional patterning process to pattern the bottom node 202 of the MIM capacitor. A second additional mask is used during a second additional patterning step to pattern the top node 204 of the MIM capacitor.
A first layer (Vx) of conductive vias 212, 214 may be formed to provide coupling between the first metal layer 208 and the second metal layer 210. In this example of a conventional MIM capacitor structure 200, the conductive vias 212, 214 are formed to couple the top node 204 of the MIM capacitor to one path of the second metal layer 210, and to couple the bottom node 202 to another path of the second metal layer 210. Because the conductive vias 212, 214 extends through the top node 204 and bottom node 206, respectively, the top node 204 and bottom node 202 of the MIM capacitor are coupled to the sidewalls of the respective conductive vias 212, 214. This type of coupling is referred to as sidewall coupling.
The use of a first additional mask and a second additional mask to pattern the top nodes and bottom nodes of MIM capacitors between metal layers in a semiconductor die may significantly increases the cost of the die. Additionally, forming MIM capacitors between two interconnect metal layers has caused packaging problems and reduced mechanical reliability.